1. Field of Invention
The present invention relates to a manufacturing method of a package structure. More particularly, the present invention relates to a manufacturing method of a quad flat no-lead (QFN) package structure.
2. Description of Related Art
The semiconductor industries are highly developed high tech industries. With the trends of electrification, electronic and semiconductor devices are widely used in the daily life, including entertainment, education, transportation and households. The design of the electrical products becomes more complex, smaller-sized, light-weight and humanized, in order to offer more convenience for the consumers. In the package structures, the leadframe is one of the most commonly used elements, applied in various package products. Based on the type of leadframes, the quad flat packages (QFP) can be categorized as quad flat package with “I” lead (QFI), quad flat package with “J” lead (QFJ) and quad flat no-lead (QFN) package. Because leads of the leadframe in the QFN package end at the edges of the chip package structure, the QFN package has a small size and is also called quad flat no-lead (QFN) chip scale package. Since the QFN package provides shorter electrical path and faster signal communication rate, the QFN package has been widely used as low pin count solutions for power elements.
FIG. 1A is a cross-sectional view of a prior QFN package structure, while FIG. 1B is the top view of the prior QFN package structure in FIG. 1A.
Referring to FIGS. 1A and 1B, the QFN package structure 100 includes a chip 110, a die pad 120, a plurality of wires 130, a plurality of leads 140 and a mold compound 150. The chip 110 has an active surface 112 and an opposite back surface 114. A plurality of bonding pads 116 is disposed on the active surface 112, while the back surface 114 is fixed to an upper surface of the die pad 120 through a silver epoxy adhesive 118. Each bonding pad 116 is electrically connected to one of the leads 140 through the wire 130. The mold compound 150 covers the chip 110, the wires 130, the upper surface of the die pad 120 and upper surfaces of the leads 140, for protecting the chip 110 and the wires 130.
As shown in FIG. 1B, the bottom surface of the die pad 120 and the lower surfaces of the leads 140 are exposed from the bottom of the mold compound 150. The ends of leads 140 terminate at the edges of the mold compound 150 and the leads 140 arranged around the die pad 120 are used as I/O pads of the QFN package structure.
It is noted that the leads 140 and the die pad 120 used in the prior art are formed integrally with the leadframe. After cutting off the frame, the leads become separated and turn into individual I/O pads around the peripheral of the die pad. However, the number of the I/O pads is limited by the space occupied by the die pad, so that the I/O pad density can not be increased.
Moreover, in the molding process, a portion of the molding compound 150 may overflows to the bottom surface of the die pad 120 or the lower surfaces of the leads 140, causing the over-glue problem. Due to the difficulties in removing over-glue, the quality of the package structure 100 is usually declined.